— At system level, intensively analyzing the system application will produce a variety of useful characteristics and provide designers valuable exploration indications. In this p...
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology ...
Mark Thompson, Hristo Nikolov, Todor Stefanov, And...
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...