Sciweavers

JCP
2008
109views more  JCP 2008»
13 years 11 months ago
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design
Abstract-- The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work ...
Debashis Mandal, T. K. Bhattacharyya
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
14 years 1 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim
ISCAS
1999
IEEE
100views Hardware» more  ISCAS 1999»
14 years 3 months ago
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis
This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (M...
Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud...
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 5 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen