DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
We present a hardware-based approach to improve the resilience of a computer system against the errors occurred in the main memory with the help of error detecting and correcting ...
DATE
2009
IEEE
2009
IEEE
A flexible layered architecture for accurate digital baseband algorithm development and verification
14 years 8 months ago
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—As multiprocessor systems are increasingly used in real-time environments, scheduling and synchronization analysis of these platforms receive growing attention. However, most kn...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Boolean satisfiability (SAT) solving has become an enabling technology with wide-ranging applications in numerous disciplines. These applications tend to be most naturally encode...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...