DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these description...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
In this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method i...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
The ability of logic transformations to enhance safety property checking has been well-established, and many industrial-strength verification solutions accordingly rely ariety of...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—In this paper we present an adaptive technique to locally adjust the frequency of processing elements on MP-SoC. The proposed method, based on Game Theory, optimizes the system ...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
DATE
2009
IEEE
14 years 8 months ago
2009
IEEE
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...