Sciweavers

DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 4 months ago
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
Nicola Concer, Salvatore Iamundo, Luciano Bononi
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 4 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 4 months ago
A real-time application design methodology for MPSoCs
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
Giovanni Beltrame, Luca Fossati, Donatella Sciuto
DATE
2009
IEEE
146views Hardware» more  DATE 2009»
14 years 4 months ago
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Abstract—Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption...
Marco Facchini, Trevor Carlson, Anselme Vignon, Ma...
DATE
2009
IEEE
114views Hardware» more  DATE 2009»
14 years 4 months ago
Hardware aging-based software metering
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...
Foad Dabiri, Miodrag Potkonjak
DATE
2009
IEEE
93views Hardware» more  DATE 2009»
14 years 4 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 4 months ago
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique
—Body sensor networks are emerging as a promising platform for healthcare monitoring. These systems are composed of battery-operated embedded devices which process physiological ...
Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozb...
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
14 years 4 months ago
Finite Precision bit-width allocation using SAT-Modulo Theory
This paper explores the use of SAT-Modulo Theory in determination of bit-widths for finite precision implementation of numerical calculations, specifically in the context of sci...
Adam B. Kinsman, Nicola Nicolici
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
14 years 4 months ago
Variable-latency design by function speculation
David Bañeres, Jordi Cortadella, Michael Ki...