Sciweavers

ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
14 years 4 months ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
14 years 4 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 4 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
ISQED
2010
IEEE
194views Hardware» more  ISQED 2010»
14 years 4 months ago
Accelerating trace computation in post-silicon debug
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...
ISQED
2010
IEEE
120views Hardware» more  ISQED 2010»
14 years 4 months ago
Methodology from chaos in IC implementation
— Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underly...
Kwangok Jeong, Andrew B. Kahng
ISQED
2010
IEEE
114views Hardware» more  ISQED 2010»
14 years 4 months ago
Toward effective utilization of timing exceptions in design optimization
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
ISQED
2010
IEEE
151views Hardware» more  ISQED 2010»
14 years 4 months ago
Leakage temperature dependency modeling in system level analysis
Abstract— As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical i...
Huang Huang, Gang Quan, Jeffrey Fan
ISQED
2010
IEEE
117views Hardware» more  ISQED 2010»
14 years 4 months ago
Variation-aware speed binning of multi-core processors
John Sartori, Aashish Pant, Rakesh Kumar, Puneet G...
ISQED
2010
IEEE
135views Hardware» more  ISQED 2010»
14 years 4 months ago
Signal probability control for relieving NBTI in SRAM cells
—Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor wh...
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 4 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...