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DSD
2009
IEEE
160views Hardware» more  DSD 2009»
14 years 17 days ago
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors
Voltage-frequency scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tas...
Anca Mariana Molnos, Kees Goossens
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
14 years 17 days ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...
DDECS
2009
IEEE
129views Hardware» more  DDECS 2009»
14 years 17 days ago
Contactless characterization of MEMS devices using optical microscopy
András Timár, György Bogn&aacut...
DDECS
2009
IEEE
107views Hardware» more  DDECS 2009»
14 years 17 days ago
Effective mars rover platform design with Hardware / Software co-design
Gábor Marosy, Zoltán Kovacs, Gyula H...
DDECS
2009
IEEE
146views Hardware» more  DDECS 2009»
14 years 17 days ago
Enhanced LEON3 core for superscalar processing
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A....
DDECS
2009
IEEE
149views Hardware» more  DDECS 2009»
14 years 17 days ago
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
Yiorgos Sfikas, Yiorgos Tsiatouhas
DATE
2009
IEEE
141views Hardware» more  DATE 2009»
14 years 17 days ago
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
Victor Lomné, Philippe Maurine, Lionel Torr...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 17 days ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
14 years 17 days ago
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
1 Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. How...
Mikael Väyrynen, Virendra Singh, Erik Larsson
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 17 days ago
Sequential logic rectifications with approximate SPFDs
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, R...