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ISPD
1999
ACM
92views Hardware» more  ISPD 1999»
14 years 1 months ago
Crosstalk constrained global route embedding
- Route Embedding, a new method for mitigating the impact of crosstalk, is presented. It modifies a set of global-route structures to prevent timing and noise-margin violations ca...
Phiroze N. Parakh, Richard B. Brown
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
14 years 1 months ago
Cycle-based Simulation with Decision Diagrams
This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the fun...
Raimund Ubar, Jaan Raik, Adam Morawiec
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
14 years 1 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
ISPD
1999
ACM
126views Hardware» more  ISPD 1999»
14 years 1 months ago
Partitioning by iterative deletion
Netlist partitioning is an important and well studied problem. In this paper, a linear time partitioning approach based on iterative deletion is presented. We use the partitioning...
Patrick H. Madden
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
14 years 1 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
14 years 1 months ago
Fast Hardware-Software Co-simulation Using VHDL Models
Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovann...
ISPD
1999
ACM
88views Hardware» more  ISPD 1999»
14 years 1 months ago
Subwavelength optical lithography: challenges and impact on physical design
We review the implications of subwavelength optical lithography for new tools and ows in the interface between layout design and manufacturability. After discussing the necessity ...
Andrew B. Kahng, Y. C. Pati
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
14 years 1 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
DATE
1999
IEEE
101views Hardware» more  DATE 1999»
14 years 1 months ago
Polynomial Methods for Allocating Complex Components
Methods for performing component matching by expressing an arithmetic specification and a bit-level description of an implementation as word-level polynomials have been demonstrat...
James Smith, Giovanni De Micheli