ISLPED
1999
ACM
14 years 1 months ago
1999
ACM
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
ISLPED
1999
ACM
14 years 1 months ago
1999
ACM
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
14 years 1 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
ISLPED
1999
ACM
14 years 1 months ago
1999
ACM
-- The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing ce...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...
ISLPED
1999
ACM
14 years 1 months ago
1999
ACM
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
ISLPED
1999
ACM
14 years 1 months ago
1999
ACM