ISPD
1999
ACM
14 years 1 months ago
1999
ACM
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
ISPD
1999
ACM
14 years 1 months ago
1999
ACM
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
ISPD
1999
ACM
14 years 1 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
ISPD
1999
ACM
14 years 1 months ago
1999
ACM
ISPD
1999
ACM
14 years 1 months ago
1999
ACM
We study alternatives to FM-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instan...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ISPD
1999
ACM
14 years 1 months ago
1999
ACM
One subtask in constraint-driven placement is enforcing a set of orientation constraints on the devices being placed. Such constraints are created in order to, for example, implem...