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DATE
1999
IEEE
127views Hardware» more  DATE 1999»
14 years 1 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
14 years 1 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
ISLPED
1999
ACM
85views Hardware» more  ISLPED 1999»
14 years 1 months ago
Non-stationary effects in trace-driven power analysis
Radu Marculescu, Diana Marculescu, Massoud Pedram
ISLPED
1999
ACM
90views Hardware» more  ISLPED 1999»
14 years 1 months ago
Way-predicting set-associative cache for high performance and low energy consumption
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way p...
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
14 years 1 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
ISLPED
1999
ACM
72views Hardware» more  ISLPED 1999»
14 years 1 months ago
The design of a low energy FPGA
George Varghese, Hui Zhang, Jan M. Rabaey
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
14 years 1 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
ISLPED
1999
ACM
86views Hardware» more  ISLPED 1999»
14 years 1 months ago
Power macro-models for DSP blocks with application to high-level synthesis
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
Subodh Gupta, Farid N. Najm
ISLPED
1999
ACM
236views Hardware» more  ISLPED 1999»
14 years 1 months ago
Modeling and automating selection of guarding techniques for datapath elements
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
William E. Dougherty, Donald E. Thomas