DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
Given a plant Å and a specification Å , the largest solution of the FSM equation Å ¯ Å Å contains all possible discrete controllers Å . Often we are interested in computin...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a gate-level repr...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE