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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 3 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
14 years 3 months ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
14 years 3 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....
DATE
2006
IEEE
83views Hardware» more  DATE 2006»
14 years 3 months ago
What lies between design intent coverage and model checking?
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. ...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 3 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 3 months ago
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs
This paper describes a fast-lock mixed-mode delaylocked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time...
Kuo-Hsing Cheng, Yu-lung Lo
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 3 months ago
Online energy-aware I/O device scheduling for hard real-time systems
Much research has focused on power conservation for the processor, while power conservation for I/O devices has received little attention. In this paper, we analyze the problem of...
Hui Cheng, Steve Goddard
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 3 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
DATE
2006
IEEE
83views Hardware» more  DATE 2006»
14 years 3 months ago
Dynamic scratch-pad memory management for irregular array access patterns
Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mus...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 3 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...