Sciweavers

DATE
2006
IEEE
117views Hardware» more  DATE 2006»
14 years 3 months ago
Activity clustering for leakage management in SPMs
This paper we proposes compiler-based leakage optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to keep only a small set of SPM regions active at a given ...
Mahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary ...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 3 months ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
14 years 3 months ago
New methods and coverage metrics for functional verification
Vasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar...
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
14 years 3 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
DATE
2006
IEEE
77views Hardware» more  DATE 2006»
14 years 3 months ago
Soft-error classification and impact analysis on real-time operating systems
This paper investigates the sensitivity of real-time systems running applications under operating systems that are subject to soft-errors. We consider applications using different...
N. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nic...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 3 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
14 years 3 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
DATE
2006
IEEE
136views Hardware» more  DATE 2006»
14 years 3 months ago
Defect tolerance of QCA tiles
Quantum dot Cellular Automata (QCA) is one of the promising technologies for nano scale implementation. The operation of QCA systems is based on a new paradigm generally referred ...
Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 3 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi