Sciweavers

DSD
2007
IEEE
164views Hardware» more  DSD 2007»
14 years 4 months ago
Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism
— Programmable multiprocessor systems-on-chip are becoming the preferred implementation platform for embedded streaming applications. This enables using more software components,...
Peter Poplavko, Twan Basten, Jef L. van Meerbergen
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
14 years 4 months ago
Evaluating the Model Accuracy in Automated Design Space Exploration
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
Kalle Holma, Mikko Setälä, Erno Salminen...
DSD
2007
IEEE
86views Hardware» more  DSD 2007»
14 years 4 months ago
On network-on-chip comparison
— This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are curre...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
DSD
2007
IEEE
88views Hardware» more  DSD 2007»
14 years 4 months ago
An Implementation of an Address Generator Using Hash Memories
An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the supe...
Tsutomu Sasao, Munehiro Matsuura
DSD
2007
IEEE
178views Hardware» more  DSD 2007»
14 years 4 months ago
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The ha...
Esra Sahin, Ilker Hamzaoglu
DSD
2007
IEEE
133views Hardware» more  DSD 2007»
14 years 4 months ago
A Serial Logarithmic Number System ALU
Serial arithmetic uses less hardware than parallel arithmetic. Serial floating point (FP) is slower than parallel FP. The Logarithmic Number System (LNS) simplifies operations, ...
Mark G. Arnold, Panagiotis D. Vouzis
DSD
2007
IEEE
142views Hardware» more  DSD 2007»
14 years 4 months ago
Decoupling of Computation and Communication with a Communication Assist
Abstract. In an embedded multiprocessor system the minimum throughput and maximum latency of real-time applications are usually derived given the worst-case execution time of the s...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 4 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
DSD
2007
IEEE
119views Hardware» more  DSD 2007»
14 years 4 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...