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DFT
2007
IEEE
135views VLSI» more  DFT 2007»
14 years 4 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
14 years 4 months ago
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
— The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access...
Bartosz Wojciechowski, Tomasz Kowalczyk, Wojciech ...
DDECS
2007
IEEE
102views Hardware» more  DDECS 2007»
14 years 4 months ago
IP Integration Overhead Analysis in System-on-Chip Video Encoder
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. ...
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
14 years 4 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 4 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
DDECS
2007
IEEE
140views Hardware» more  DDECS 2007»
14 years 4 months ago
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
Manuel G. Gericota, Luís F. Lemos, Gustavo ...
DDECS
2007
IEEE
93views Hardware» more  DDECS 2007»
14 years 4 months ago
Manifestation of Precharge Faults in High Speed DRAM Devices
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
DDECS
2007
IEEE
86views Hardware» more  DDECS 2007»
14 years 4 months ago
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
Lukás Sekanina
DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
14 years 4 months ago
New Strategies for System-Level Design
Daniel D. Gajski
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 4 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...