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DSD
2007
IEEE
140views Hardware» more  DSD 2007»
14 years 3 months ago
Pseudo-Random Pattern Generator Design for Column-Matching BIST
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
Petr Fiser
DSD
2007
IEEE
217views Hardware» more  DSD 2007»
14 years 3 months ago
Component-Based Hardware/Software Co-Simulation
Developing highly efficient and reliable embedded systems demands hardware/software (HW/SW) co-design and, therefore, co-simulation. In order to be highly configurable, embedded...
Ping Hang Cheung, Kecheng Hao, Fei Xie
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
14 years 3 months ago
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
DSD
2007
IEEE
75views Hardware» more  DSD 2007»
14 years 3 months ago
Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip
Pekka Rantala, Jouni Isoaho, Hannu Tenhunen
DSD
2007
IEEE
83views Hardware» more  DSD 2007»
14 years 3 months ago
Hierarchical Identification of Untestable Faults in Sequential Circuits
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kru...
DSD
2007
IEEE
150views Hardware» more  DSD 2007»
14 years 3 months ago
Adaptive Distance Estimation and Localization in WSN using RSSI Measures
Abstract—Localization is one of the most challenging and important issues in wireless sensor networks (WSNs), especially if cost-effective approaches are demanded. In this paper,...
Abdalkarim Awad, Thorsten Frunzke, Falko Dressler
DSD
2007
IEEE
96views Hardware» more  DSD 2007»
14 years 3 months ago
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties
Jaroslav Skarvada, Tomas Herrman, Zdenek Kot&aacut...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
14 years 3 months ago
Latency Minimization for Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) are a very useful means for modeling and analyzing streaming applications. Some performance indicators, such as throughput, have been studied b...
Amir Hossein Ghamarian, Sander Stuijk, Twan Basten...
DSD
2007
IEEE
87views Hardware» more  DSD 2007»
14 years 3 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 3 months ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...