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DATE
2007
IEEE
103views Hardware» more  DATE 2007»
14 years 3 months ago
Flexible hardware reduction for elliptic curve cryptography in GF(2m)
In this paper we discuss two ways to provide flexible hardware support for the reduction step in Elliptic Curve Cryptography in binary fields (GF(2m )). In our first approach w...
Steffen Peter, Peter Langendörfer, Krzysztof ...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 3 months ago
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
We propose a robust circuit-based Boolean Satisfiability (SAT) solver, QuteSAT, that can be applied to complex circuit netlist structure. Several novel techniques are proposed in ...
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 3 months ago
Automatic synthesis of compressor trees: reevaluating large counters
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
Ajay K. Verma, Paolo Ienne
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 3 months ago
A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks
Pawel Gburzynski, Bozena Kaminska, Wladek Olesinsk...
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
14 years 3 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
14 years 3 months ago
Design fault directed test generation for microprocessor validation
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher p...
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V...
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
14 years 3 months ago
An area optimized reconfigurable encryptor for AES-Rijndael
Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Sant...
DATE
2007
IEEE
127views Hardware» more  DATE 2007»
14 years 3 months ago
A calculator for Pareto points
This paper presents the Pareto Calculator, a tool for compositional computation of Pareto points, based on the algebra of Pareto points. The tool is a useful instrument for multidi...
Marc Geilen, Twan Basten
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 3 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...