DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...