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DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 3 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 3 months ago
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, ...
DATE
2007
IEEE
88views Hardware» more  DATE 2007»
14 years 3 months ago
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 3 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
2007
IEEE
65views Hardware» more  DATE 2007»
14 years 3 months ago
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 3 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
14 years 3 months ago
Temperature and voltage aware timing analysis: application to voltage drops
B. Lasbouygues, Robin Wilson, Nadine Azémar...
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 3 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...