Sciweavers

DATE
2007
IEEE
91views Hardware» more  DATE 2007»
14 years 3 months ago
Remote testing and diagnosis of System-on-Chips using network management frameworks
This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (...
Oussama Laouamri, Chouki Aktouf
DATE
2007
IEEE
66views Hardware» more  DATE 2007»
14 years 3 months ago
Yield-aware placement optimization
ct In this paper we describe a methodology addressing the issue of avoiding yield hazardous cell abutments during placement. This is made possible by accurate characterization of t...
Paolo Azzoni, Massimo Bertoletti, Nicola Dragone, ...
DATE
2007
IEEE
77views Hardware» more  DATE 2007»
14 years 3 months ago
Method for reducing jitter in multi-gigahertz ATE
Controlling jitter on a picosecond (or smaller) time scale has become one of the most difficult challenges for testing multi-gigahertz systems. In this paper we present a novel me...
David C. Keezer, Dany Minier, Patrice Ducharme
DATE
2007
IEEE
119views Hardware» more  DATE 2007»
14 years 3 months ago
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling
Lasers can be used by hackers to situations to inject faults in circuits and induce security flaws. On-line detection mechanisms are classically proposed to counter such attacks, ...
Régis Leveugle, Abdelaziz Ammari, V. Maingo...
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 3 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
DATE
2007
IEEE
110views Hardware» more  DATE 2007»
14 years 3 months ago
Accurate timing analysis using SAT and pattern-dependent delay models
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bah...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 3 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
14 years 3 months ago
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Paul Wielage, Erik Jan Marinissen, Michel Altheime...