DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Software implementations of modern block ciphers often require large lookup tables along with code size increasing optimizations like loop unrolling to reach peak performance on g...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE