ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. ...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. Dictionary-based code c...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
— In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, ea...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE