ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Analog and mixed-signal CAD looks like a nice success story: there's been significant research in building design automation tools since the late 80's, and commercial to...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
This paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the GHZ range. Most of the previous work focused mainly o...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
– Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
With semiconductor industry's aggressive march towards 45nm
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exace...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...