ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer circuit design. High voltages resulted from ESD might cause high current densitie...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix L. While there are...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical planarization (CMP) to remove excess of deposited oxide and attain a planar...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
ICCAD
2006
IEEE
14 years 8 months ago
2006
IEEE