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ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
14 years 9 months ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
14 years 9 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
14 years 9 months ago
In-Line Interrupt Handling for Software-Managed TLBs
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
Aamer Jaleel, Bruce L. Jacob
ICCD
2001
IEEE
176views Hardware» more  ICCD 2001»
14 years 9 months ago
BDD Variable Ordering by Scatter Search
Reduced Ordered Binary Decision Diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI Design Automation. ...
William N. N. Hung, Xiaoyu Song
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
14 years 9 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 9 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ICCD
2001
IEEE
77views Hardware» more  ICCD 2001»
14 years 9 months ago
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...
John W. Haskins Jr., Kevin Skadron
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 9 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 9 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...