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    EUROPAR
    2005
    Springer
    138views Distributed And Parallel Com...» more  EUROPAR 2005»
    Improving Instruction Delivery with a Block-Aware ISA
    14 years 5 months ago
    Improving Instruction Delivery with a Block-Aware ISA
    Download  csl.stanford.edu
    Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
    Ahmad Zmily, Earl Killian, Christos Kozyrakis
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    IPPS
    2005
    IEEE
    109views Distributed And Parallel Com...» more  IPPS 2005»
    Effective Instruction Prefetching via Fetch Prestaging
    14 years 5 months ago
    Effective Instruction Prefetching via Fetch Prestaging
    Download  ics07.ac.upc.edu
    As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
    Ayose Falcón, Alex Ramírez, Mateo Va...
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    GLVLSI
    2005
    IEEE
    124views VLSI» more  GLVLSI 2005»
    A first look at the interplay of code reordering and configurable caches
    14 years 5 months ago
    A first look at the interplay of code reordering and configurable caches
    Download  www.cs.ucr.edu
    The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
    Ann Gordon-Ross, Frank Vahid, Nikil Dutt
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    ASPLOS
    2006
    ACM
    107views Programming Languages» more  ASPLOS 2006»
    Software-based instruction caching for embedded processors
    14 years 5 months ago
    Software-based instruction caching for embedded processors
    Download  groups.csail.mit.edu
    While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
    Jason E. Miller, Anant Agarwal
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    IEEEPACT
    2007
    IEEE
    178views Distributed And Parallel Com...» more  IEEEPACT 2007»
    Call-chain Software Instruction Prefetching in J2EE Server Applications
    14 years 5 months ago
    Call-chain Software Instruction Prefetching in J2EE Server Applications
    Download  www.cs.ucsb.edu
    We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
    Priya Nagpurkar, Harold W. Cain, Mauricio J. Serra...
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    GLVLSI
    2008
    IEEE
    112views VLSI» more  GLVLSI 2008»
    Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
    14 years 6 months ago
    Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
    Download  qir.kyushu-u.ac.jp
    Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
    Maziar Goudarzi, Tohru Ishihara
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    DATE
    2008
    IEEE
    117views Hardware» more  DATE 2008»
    CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches
    14 years 6 months ago
    CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches
    Download  www2.cs.ucy.ac.cy
    Cache-Content-Duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different t...
    Marios Kleanthous, Yiannakis Sazeides
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    ICCD
    2001
    IEEE
    120views Hardware» more  ICCD 2001»
    Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
    14 years 8 months ago
    Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
    Download  www.ics.uci.edu
    Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
    Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
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    DAC
    2009
    ACM
    150views Computer Architecture» more  DAC 2009»
    A DVS-based pipelined reconfigurable instruction memory
    15 years 16 days ago
    A DVS-based pipelined reconfigurable instruction memory
    Download  esl.cse.nsysu.edu.tw
    Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
    Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
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