ISQED
2010
IEEE
14 years 5 months ago
2010
IEEE
A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary met...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
- In this paper, we propose a thermal-aware job allocation and scheduling algorithm for three-dimensional (3D) chip multiprocessor (CMP). The proposed algorithm assigns hot jobs to...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
Abstract—Silicon debug poses a unique challenge to the engineer because of the limited access to internal signals of the chip. Embedded hardware such as trace buffers helps overc...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
— Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underly...
ISQED
2010
IEEE
14 years 7 months ago
2010
IEEE
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...