- In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
— A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator’s steady-s...
Igor Vytyaz, David C. Lee, Un-Ku Moon, Kartikeya M...
In this paper we describe a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parametric s...
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltag...