Sciweavers

ASPDAC
2011
ACM
167views Hardware» more  ASPDAC 2011»
13 years 2 months ago
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
- In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaus...
ET
2002
64views more  ET 2002»
13 years 11 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
14 years 5 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
14 years 5 months ago
Parameter variation analysis for voltage controlled oscillators in phase-locked loops
— A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator’s steady-s...
Igor Vytyaz, David C. Lee, Un-Ku Moon, Kartikeya M...
DATE
2008
IEEE
137views Hardware» more  DATE 2008»
14 years 5 months ago
SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
In this paper we describe a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parametric s...
Jorge Fernandez Villena, Luis Miguel Silveira
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
14 years 5 months ago
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...
DAC
2003
ACM
15 years 5 days ago
Parameter variations and impact on circuits and microarchitecture
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltag...
Shekhar Borkar, Tanay Karnik, Siva Narendra, James...