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ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
14 years 4 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ISCAS
2002
IEEE
81views Hardware» more  ISCAS 2002»
14 years 4 months ago
Concept of phase-noise tuning of bipolar voltage-controlled oscillators
So far, oscillators have been designed to perform a specific task while the key parameters such as phase-noise and power consumption are set by the hardware design and not by the ...
Aleksandar Tasic, Wouter A. Serdijn
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
14 years 4 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 4 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
14 years 4 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
APCCAS
2002
IEEE
95views Hardware» more  APCCAS 2002»
14 years 4 months ago
Reducing power consumption of instruction ROMs by exploiting instruction frequency
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the sw...
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
14 years 4 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
14 years 4 months ago
Ultra low-power 12-bit SAR ADC for RFID applications
The design and first measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are o...
Daniela De Venuto, Eduard Stikvoort, David Tio Cas...
ICS
2003
Tsinghua U.
14 years 4 months ago
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
Power consumption is a critical issue in interconnection network design, driven by power-related design constraints, such as thermal and power delivery design. Usually, off-line w...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
14 years 4 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...