Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Abstract--As the supply voltage to a standard CMOS opamp is reduced, the input common mode range and the output swing get reduced drastically. Special biasing circuits have to be u...
This paper presents an accurate switched-current multiplier, designed for 3.3V supply voltage, performing 0.625M multiplications per second with a maximum nonlinearity of 0.94%. Th...
Domine Leenaerts, G. H. M. Joordens, Johannes A. H...
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling pro...
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
This paper presents a real-time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks wi...
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...