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CAL
2004
13 years 11 months ago
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction
We compare techniques that dynamically scale the voltage of individual network links to reduce power consumption with an approach in which all links in the network are set to the s...
J. M. Stine, N. P. Carter
GLVLSI
2010
IEEE
168views VLSI» more  GLVLSI 2010»
14 years 1 days ago
A revisit to voltage partitioning problem
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi G...
SAC
2010
ACM
14 years 1 days ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
ISLPED
2007
ACM
84views Hardware» more  ISLPED 2007»
14 years 1 months ago
Towards a software approach to mitigate voltage emergencies
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One a...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
14 years 1 months ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
14 years 3 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
DAC
2010
ACM
14 years 3 months ago
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme
System optimization techniques based on dynamic voltage scaling (DVS) are widely used with the aim of reducing processor energy consumption. Inter-task DVS assigns the same voltag...
Weixun Wang, Prabhat Mishra
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
14 years 3 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
14 years 3 months ago
Voltage Island Generation under Performance Requirement for SoC Designs
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
Wai-Kei Mak, Jr-Wei Chen
VTS
1997
IEEE
90views Hardware» more  VTS 1997»
14 years 4 months ago
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a...
Jonathan T.-Y. Chang, Edward J. McCluskey