Sciweavers

VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 6 months ago
Implementing a Scheme for External Deterministic Self-Test
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
14 years 6 months ago
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
VTS
2005
IEEE
178views Hardware» more  VTS 2005»
14 years 6 months ago
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures
Luigi Dilillo, Patrick Girard, Serge Pravossoudovi...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 6 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
VTS
2005
IEEE
90views Hardware» more  VTS 2005»
14 years 6 months ago
Soft Error Mitigation for SRAM-Based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
VTS
2005
IEEE
106views Hardware» more  VTS 2005»
14 years 6 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
VTS
2005
IEEE
145views Hardware» more  VTS 2005»
14 years 6 months ago
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements
The power supply transient signal (IDDT) method that we propose for defect detection analyze regional signal variations introduced by defects at a set of power supply pads on the ...
Dhruva Acharyya, Jim Plusquellic