33 search results - page 5 / 7 » A Power Minimization Technique for Arithmetic Circuits by Ce... |
DATE
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
ISLPED
2004
ACM
14 years 27 days ago
2004
ACM
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...