74 search results - page 3 / 15 » A VHDL-based bus model for multi-PCB system design |
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...