179 search results - page 16 / 36 » A new test pattern generation method for delay fault testing |
ITC
1998
IEEE
14 years 29 days ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
VTS
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
ITC
1997
IEEE
14 years 28 days ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...