69 search results - page 9 / 14 » Buffer insertion for clock delay and skew minimization |
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for ...
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
TVLSI
2010
13 years 2 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ICCAD
1999
IEEE
14 years 4 days ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...