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DAC
2002
ACM
14 years 10 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
14 years 4 months ago
Fundamental Data Retention Limits in SRAM Standby Experimental Results
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
14 years 4 months ago
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
ICCAD
2002
IEEE
127views Hardware» more  ICCAD 2002»
14 years 6 months ago
Leakage power modeling and reduction with data retention
Weiping Liao, Joseph M. Basile, Lei He
VTS
2005
IEEE
178views Hardware» more  VTS 2005»
14 years 3 months ago
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures
Luigi Dilillo, Patrick Girard, Serge Pravossoudovi...