85 search results - page 5 / 17 » Designing Memory Subsystems Resilient to Process Variations |
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper, we have analyzed ond modeled the fiilure probabilities ofSRAM cells due to process parameter variations. A method to predict the yield of a memoiy chip based on the...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
JRTIP
2008
13 years 7 months ago
2008
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
SBACPAD
2003
IEEE
14 years 24 days ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...