375 search results - page 4 / 75 » Explicit gate delay model for timing evaluation |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
ICFEM
2010
Springer
13 years 6 months ago
2010
Springer
The correct behavior of a service composition depends on the appropriate coordination of its services. According to the idea of channelbased coordination, services exchange message...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...