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ARCS
2008
Springer
13 years 9 months ago
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...
Joachim Keinert, Christian Haubelt, Jürgen Te...
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
14 years 4 months ago
CMOS Comparators for High-Speed and Low-Power Applications
— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present h...
Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil...
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
14 years 27 days ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
13 years 12 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
DATE
1997
IEEE
95views Hardware» more  DATE 1997»
13 years 12 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...