1773 search results - page 38 / 355 » High-level power estimation |
118
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GLVLSI
2007
IEEE
15 years 9 months ago
2007
IEEE
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
121
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ICASSP
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
109
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DATE
2000
IEEE
15 years 7 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
125
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ISLPED
1995
ACM
15 years 6 months ago
1995
ACM
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL . Such a high-level power estimation capability is r...