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ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
15 years 10 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
DAC
1996
ACM
15 years 8 months ago
Improving the Efficiency of Power Simulators by Input Vector Compaction
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, ...
TIM
2010
144views Education» more  TIM 2010»
14 years 10 months ago
A Decentralized Observer for Ship Power System Applications: Implementation and Experimental Validation
In the last few years, the growing complexity of the electrical power networks, mainly due to the increased use of electronic converters together with the requirements of a higher ...
Andrea Benigni, Gabriele D'Antona, U. Ghisla, Anto...
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 10 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
15 years 10 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran