17 search results - page 2 / 4 » Integration of Clock Skew and Register Delays into a Retimin... |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...