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ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
14 years 4 months ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
14 years 1 days ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
DATE
2007
IEEE
74views Hardware» more  DATE 2007»
14 years 2 months ago
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosi...