588 search results - page 43 / 118 » Modeling and Verifying Circuits Using Generalized Relative T... |
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
SLIP
2005
ACM
14 years 1 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...