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DATE
2005
IEEE
160views Hardware» more  DATE 2005»
14 years 1 months ago
SOC Testing Methodology and Practice
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
Cheng-Wen Wu
DELTA
2008
IEEE
14 years 1 months ago
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
TVLSI
1998
123views more  TVLSI 1998»
13 years 7 months ago
On-line fault detection for bus-based field programmable gate arrays
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
N. R. Shnidman, William H. Mangione-Smith, Miodrag...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 11 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
DATE
2010
IEEE
120views Hardware» more  DATE 2010»
14 years 15 days ago
Memory testing with a RISC microcontroller
—Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not ...
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdiou...