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» Overview on Low Power SoC Design Technology
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ISPD
2010
ACM
160views Hardware» more  ISPD 2010»
14 years 2 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 8 months ago
High-Performance Power Grids For Nanometer Technologies
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
Sachin S. Sapatnekar
SOCC
2008
IEEE
121views Education» more  SOCC 2008»
14 years 2 months ago
Low power 8T SRAM using 32nm independent gate FinFET technology
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
DSD
2006
IEEE
183views Hardware» more  DSD 2006»
14 years 1 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 8 months ago
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Pan...