60 search results - page 7 / 12 » Polysynchronous stochastic circuits |
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
AAAI
1997
13 years 10 months ago
1997
We report on the performance of an enhanced version of the “Davis-Putnam” (DP) proof procedure for propositional satisfiability (SAT) on large instances derived from realworld...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
DATE
2000
IEEE
14 years 29 days ago
2000
IEEE
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...