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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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DAC
2007
ACM
14 years 8 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
ITC
2000
IEEE
55views Hardware» more  ITC 2000»
14 years 7 days ago
Low power BIST design by hypergraph partitioning: methodology and architectures
Patrick Girard, Christian Landrault, Loïs Gui...
HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 4 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He